The subject invention is generally directed to sample-and-hold circuitry, and is directed more particularly to droop compensation circuitry for sample-and-hold circuits.
Sample-and-hold circuits are utilized in various applications including analog-to-digital conversion of video signals, which generally requires the use of a sample-and-hold circuit that is capable of maintaining a substantially constant output during the course of the conversion process.
A video speed sample-and-hold circuit generally consists of a buffer amplifier followed by an electronic sampling switch, a capacitor to hold the sampled voltages and an output amplifier to read the capacitor voltage into an analog-to-digital converter. Droop occurs when charge leaks off of the capacitor during the hold phase of the sampling cycle. Excessive droop interferes with accurate quantization by the analog-to-digital converter.
The problem of sample-and-hold droop has been addressed in a number of different ways. The most obvious is simply to use a hold amplifier for which the input bias current is negligibly small. Amplifiers with field-effect input stage transistors have almost zero input current, but they generate too much noise to be useful in broadband, high resolution converters. Bipolar transistors generate much less noise, but their base currents are of appreciable magnitude and are also temperature dependent. The problem is compounded by the need to keep the hold capacitance small to facilitate fast acquisition of new voltage samples within the current limitations imposed by realizable sampling switches and buffer amplifiers. Furthermore, if the hold amplifier is to settle quickly, its transistors bias currents, including the input base current, will tend to be larger.
Bias current cancellation schemes have been devised which attempt to develop a current source that can be connected to the hold node to supply exactly the amount of current demanded by the hold amplifier. Temperature tracking is maintained by use of monolithic construction and matching transistor geometries. The weakness of this approach is that it requires the use of a transistor current mirror, and at high video slew rates significant charge can be pumped into the mirror structure through parasitic capacitance. This manifests itself as rapidly deteriorating harmonic distortion performance for input video frequencies approaching half the sample rate.